These bits determine the number of GCLK_WDT clock cycles between the start of the
watchdog time-out period and the generation of the Early Warning interrupt.
These bits are loaded from User Configuration FUCFG0 at start-up.
| Value | Name | Description |
|---|
| 0x0 | CYC8 | 8 clock cycles |
| 0x1 | CYC16 | 16 clock cycles |
| 0x2 | CYC32 | 32 clock cycles |
| 0x3 | CYC64 | 64 clock cycles |
| 0x4 | CYC128 | 128 clock cycles |
| 0x5 | CYC256 | 256 clock cycles |
| 0x6 | CYC512 | 512 clock cycles |
| 0x7 | CYC1024 | 1024 clock cycles |
| 0x8 | CYC2048 | 2048 clock cycles |
| 0x9 | CYC4096 | 4096 clock cycles |
| 0xA | CYC8192 | 8192 clock cycles |
| 0xB | CYC16384 | 16384 clock cycles |
