21.1 Overview

The Main Clock (MCLK) controls the generation of the device synchronous clocks.

Using a clock provided by the Generic Clock Generator 0 Module (GCLK_MAIN), the MCLK provides synchronous clocks to the CPU, the three Advanced Peripheral Buses (APB), the Advanced High-performance Buses (AHB), and the peripherals connected to these buses.

The synchronous system clocks are divided into 3 clock domains, each can run at different frequencies. The generated clocks can be masked for individual modules, enabling the user to minimize power consumption.