21.2 Features

  • Clock source: GCLK_MAIN derived from GCLK0
  • Three clock domains:
    • 1, 2, 4, 8, 16, 32, 64, 128 independent division factors from GCLK_MAIN
    • Clock domain 0: Generates individual clocks running at fCD0 frequency for CPU, AHB, APB0/1, and all peripherals connected to them(1)
    • Clock domain 1: Generates individual clocks running at fCD1 frequency for APB2 and all peripherals connected to it (1)
    • Clock domain 2: Generates a clock running at fCD2 dedicated for the MBISTINTF module (1)
  • Clock domain divider update on the fly
  • Peripheral-level clock gating through individual mask bits
Note:
  1. Refer to the Peripherals Configuration Summary for the list of peripherals and the associated clock domain, and clock mask register and index.