33.13 Peripheral Dependencies
| Peripheral Name | Base Address |
NVIC IRQ Index:Source |
MCLK AHB/APB Clock Enable Bus:Register:Bit |
GCLK Peripheral Channel Control Register |
PAC Peripheral Identifier PERID:Register:Bit |
DMA Trigger Index:Source |
Event System Type:Event: Register:Path | Power Domain |
|---|---|---|---|---|---|---|---|---|
| PORT | 0x44800000 |
41 : NSCHK0/NSCHK1/NSCHK2/NSCHK3 |
APB: CLKMSK[0] MASK27 | --- |
20 STATUS0 PERID20 |
Users: EV0: USER[2],Resynch EV1: USER[3],Resynch EV2: USER[4],Resynch EV3: USER[5],Resynch |
PD_CORE_SW |