28.1 Overview

The Power Manager (PM) controls the sleep modes and the power domain gating of the device

Various sleep modes are provided in order to fit power consumption requirements. This enables the PM to stop unused modules in order to save power. In active mode, the CPU is executing application code. When the device enters a sleep mode, program execution is stopped and some modules and clock domains are automatically switched off by the PM according to the sleep mode. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals and all enabled reset sources (SYSRST is not enabled in sleep mode) can restore the device from a sleep mode to active mode.

Performance level technique consists of adjusting the regulator output voltage to reduce power consumption. The user can select on the fly the performance level configuration which best suits the application.

The application configures which power domains are on and off during standbyand hibernate sleep modes. When the application selects to enter a sleep mode, hardware automatically enters that mode when it detects no activity. Based on activity monitoring, power domain gating is managed automatically by hardware without software intervention. This technique is transparent for the application while minimizing the static consumption.

In hibernate mode, the PM allows retaining the state of the I/O lines, preventing I/O lines from toggling during wake-up.