31.4 Peripheral Dependencies
| Peripheral Name | Base Address |
NVIC IRQ Index:Source |
MCLK AHB/APB Clock Enable Bus:Register:Bit |
GCLK Peripheral Channel Control Register |
PAC Peripheral Identifier PERID:Register:Bit |
DMA Trigger Index:Source |
Event System Type:Event: Register:Path | Power Domain |
|---|---|---|---|---|---|---|---|---|
| FCR | 0x44002000 |
0 : FCR |
AHB: CLKMSK[0] MASK1 | --- |
1 STATUS0 PERID1 |
PD_CORE_SW |