27.2 Features

The SUPC controls the following analog supply elements:

  • Voltage Regulator System
    • Capless voltage regulators called VREGSW is used in active, idle and standby mode, to supply PD_CORE_SW power domain.
    • Capless voltage regulator called VREGRAM used in active, idle, standby and hibernate mode to supply VDDCORE_RAM domain and PLL
  • Voltage Reference System (Bandgap)
    • Reference voltage for ADC
    • Temperature sensor
    • Low power mode in standby sleep mode
    • Charge Pump for I/O pad and analog cells as PTC/AC/ADC in case of low VDD voltage
  • 3.3V Brown-out Reset (BOR) Detector
    • Three instances of BOR are used when calibrated to monitor VDDIO, AVDD and VDDREG power supply voltages, during Power Up, Active mode and Standby Sleep mode
    • Programmable threshold value loaded from USER CFG page at startup
    • Triggers resets
    • Operating modes:Continuous mode and Low power mode in standby sleep mode.
  • 3.3V Low-Power Brown-out Reset (DCBOR)
    • Threshold values loaded from USER CFG page of CFM Flash Memory
    • Triggers resets
    • Operating modes: Continuous mode and Sampled mode (with programmable sampling frequency)
  • 1.2V Brown-Out Reset (BOR12)
    • Monitors VDDCORE power supply voltage
    • Tightly coupled with the capless regulator
    • Triggers resets
  • 3.3V Programmable Low-voltage Detector
    • Monitors VDDREG
    • Configurable threshold and direction
    • Can trigger Interrupt
  • Output pins
    • Pin toggling on RTC event or by SUPC in Backup mode