38.5.6.3 Dedicated Digital Comparator
The ADC module has a dedicated Digital Comparator that can alert the application to the capture and conversion of input signals that match predefined criterion(s). When an input conversion produces a “hit” the flag INTFLAG.CMPHIT is set, which can optionally fire the interrupt if INTENSET.CMPHIT is set. The index, k, of the input channel that produce the “hit” is identified in the INTENSET.CMPINTID[3:0] field.
The Digital Comparator must be enabled by setting CMPCTRL.CMPEN. Only those input channels that have the associated CHNCMPENk bit set are included in the comparator scans.
The CMPCTRL register supports these comparisons directly:
bit 29
IEHIHI: Enable Comparison - High Limit, Active High:Setting this bit enables comparison events ADCMPHI ≤ ADC value
bit 28
IEHILO: Enable Comparison - High Limit, Active Low:Setting this bit enables comparison events ADC value < ADCMPHI
bit 15
IEBTWN: Enable Comparison - Active Between Limits:Setting this bit enables comparison events ADCMPLO ≤ ADC Value < ADCMPHI
bit 14
IELOHI: Enable Comparison - Low Limit, Active High:Setting this bit enables comparison events ADCMPLO ≤ ADC Value
bit 13
IELOLO: Enable Comparison - Low Limit, Active Low:Setting this bit enables comparison events ADC Value < ADCMPLO
Since setting more than one of the IE* bits produces a condition that is the and of all conditions enabled, it is not a recommended configuration.