29.7.1 Reset Cause
Note: Only one bit is set at any one time. This register only reflects the last
event.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | RCAUSE |
| Offset: | 0x0 |
| Reset: | None |
| Property: | R |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LOCKUP | BACKUP | ||||||||
| Access | R | R | |||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SYST | WDT | EXT | BORVDDIO | BORVDDA | BORVDDREG | PORCORE | POR | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset |
Bit 9 – LOCKUP The CPU was reset because a LOCKUP Reset from main cpu has occurred.
CPU has entered lockup state. (for details, refer to the “Arm® Cortex™ Technical Reference Manual” available at www.arm.com).
Bit 8 – BACKUP The CPU was reset because a backup exit condition has occurred.
Reset cause when leaving Backup or Hibernate mode due to wake event (RTC).
Bit 7 – SYST The CPU was reset because a software reset (system reset) from main CPU has been performed
Reset generated by a System Reset Request by the CPU by asserting the SYSRESETREQ bit located in the Reset Control register of the CPU (for details, refer to the “Arm® Cortex™ Technical Reference Manual” available at www.arm.com).
Bit 6 – WDT The CPU was reset due to a watchdog reset
Reset generated by Watchdog Timer.
Bit 5 – EXT The CPU was reset due to the RESET pin being asserted.
Reset by the RESET pin driven low.
Bit 4 – BORVDDIO The CPU was reset due to the VDDIO supply voltage being lower than the brown-out threshold level 3.3 V.
Reset generated by VDDIO BOR Detector.
Bit 3 – BORVDDA The CPU was reset due to the VDDA supply voltage being lower than the brown-out threshold level 3.3 V.
Reset generated by VDDA BOR Detector.
Bit 2 – BORVDDREG The CPU was reset due to the VDDREG supply voltage being lower than the brown-out threshold level 3.3 V.
Reset by VDDREG BOR Detector.
Bit 1 – PORCORE The CPU was reset due to the supply voltage being lower than the brown-out threshold level 1.2 V.
Reset by Core Power-on Reset.
Bit 0 – POR The CPU was reset due to the supply voltage being lower than the power-on level
Reset generated by Power-on Reset.