12.2.1 Block Diagram - CLKCTRL

Figure 12-1. CLKCTRL Block Diagram
The clock system consists of the main clock and clocks derived from the main clock, as well as several asynchronous clocks:
  • The Main Clock (CLK_MAIN) is always running in Active mode and Idle sleep mode. If requested, it will also run in Standby sleep mode.
  • CLK_MAIN is prescaled and distributed by the clock controller:
    • CLK_CPU is used by the CPU, the SRAM, and the Nonvolatile Memory Controller (NVMCTRL)
    • CLK_PER is used by all peripherals that are not listed under asynchronous clocks and can also be routed to the CLKOUT pin
    • All clock sources can be used as the main clock
  • Clocks running asynchronously to the main clock domain:
    • CLK_WDT is used by the Watchdog Timer (WDT). It is requested when the WDT is enabled.
    • CLK_BOD is used by the Brown-out Detector (BOD). It is requested when the BOD is enabled in Sampled mode. The alternative clock source is controlled by a fuse.
    • CLK_RTC is used by the Real-Time Counter (RTC) and the Periodic Interrupt Timer (PIT). It is requested when the RTC/PIT is enabled. The clock source for CLK_RTC may be changed only if the peripheral is disabled.
    • CLK_CCL is used by the Configurable Custom Logic (CCL). It is requested when the CCL is enabled. The clock source may be changed only if the peripheral is disabled.

The clock source for the main clock domain is configured by writing to the Clock Select (CLKSEL) bit field in the Main Clock Control A (CLKCTRL.MCLKCTRLA) register. This register has Configuration Change Protection (CCP), and the appropriate key must be written to the CCP register before writing to the CLKSEL bit field. The asynchronous clock sources are configured by the registers in the respective peripheral.