3.1 I/O Multiplexing


VQFN/TQFP 32-Pin	VQFN 28-Pin	SSOP/SDIP 28-Pin	VQFN 20-Pin	SSOP 20-Pin	SOIC/TSSOP 14-Pin	Pin Name⁽¹⁾	Special	ADC0	AC0	PTC	USART0	SPI0	TWI0⁽³⁾	TCE0	TCBn	EVSYS	CCL-LUTn
30	26	22	17	4	4	PA0	XTAL32K1 EXTCLK			X0/Y0	TxD	MOSI⁽²⁾	SDA (HC)⁽²⁾	WO0			0, IN0 0, IN0⁽²⁾
31	27	23	18	5	5	PA1	XTAL32K2			X1/Y1	RxD	MISO⁽²⁾	SCL (HC)⁽²⁾	WO1			0, IN1 0, IN1⁽²⁾
32	28	24	19	6	-	PA2		AIN22		X2/Y2	AUX0 TxD⁽²⁾		SDA (HC) SDA (HC)⁽²⁾	WO2	0, WO	EVOUTA	0, IN2 0, IN2⁽²⁾
1	1	25	20	7	-	PA3		AIN23		X3/Y3	AUX1 RxD⁽²⁾		SCL (HC) SCL (HC)⁽²⁾		1, WO		0, OUT
2	2	26	1	8	-	PA4		AIN24		X4/Y4	TxD⁽²⁾	MOSI
3	3	27	2	9	-	PA5		AIN25		X5/Y5	RxD⁽²⁾	MISO
4	4	28	3	10	-	PA6		AIN26		X6/Y6	AUX0⁽²⁾	SCK					0, OUT⁽²⁾
5	5	1	4	11	-	PA7	CLKOUT	AIN27	OUT	X7/Y7	AUX1⁽²⁾	SS				EVOUTA⁽²⁾
6	6	2	5	12	6	PC0				X48/Y48		SCK⁽²⁾ MOSI⁽²⁾		WO0⁽²⁾			1, IN0
7	7	3	6	13	7	PC1				X49/Y49	TxD⁽²⁾	SS⁽²⁾ MISO⁽²⁾ MOSI⁽²⁾		WO1⁽²⁾			1, IN1
8	8	4	7	14	8	PC2				X50/Y50	RxD⁽²⁾	SCK⁽²⁾ MISO⁽²⁾	SDA (C) SDA (HC)⁽²⁾ SDA (C)⁽²⁾	WO2⁽²⁾		EVOUTC	1, IN2
9	9	5	8	15	9	PC3				X51/Y51	AUX0⁽²⁾	SS⁽²⁾ SCK⁽²⁾	SCL (C) SCL (HC)⁽²⁾ SCL (C)⁽²⁾				1, OUT
10	10	6	-	-	-	PD0		AIN0	ACINN1	X16/Y16				WO0⁽²⁾			2, IN0 2, IN0⁽²⁾
11	11	7	-	-	-	PD1		AIN1		X17/Y17				WO1⁽²⁾			2, IN1 2, IN1⁽²⁾
12	12	8	-	-	-	PD2		AIN2	ACINP0	X18/Y18				WO2⁽²⁾		EVOUTD	2, IN2 2, IN2⁽²⁾
13	13	9	-	-	-	PD3		AIN3	ACINN0	X19/Y19							2, OUT
14	14	10	9	16	10	PD4	EXTCINT0⁽⁴⁾	AIN4		X20/Y20	TxD⁽²⁾	MOSI⁽²⁾
15	15	11	10	17	11	PD5	EXTCINT1⁽⁴⁾	AIN5		X21/Y21	RxD⁽²⁾	MISO⁽²⁾
16	16	12	11	18	12	PD6		AIN6	ACINP3	X22/Y22	AUX0⁽²⁾	SCK⁽²⁾					2, OUT⁽²⁾
17	17	13	12	19	13	PD7	EXTVREF0	AIN7	ACINN2	X23/Y23	AUX1⁽²⁾	SS⁽²⁾				EVOUTD⁽²⁾
18	18	14	13	20	14	VDD
19	19	15	14	1	1	GND
20	20	16	-	-	-	PF0		AIN16		X32/Y32				WO0⁽²⁾			3, IN0
21	21	17	-	-	-	PF1		AIN17		X33/Y33				WO1⁽²⁾			3, IN1
22	-	-	-	-	-	PF2		AIN18		X34/Y34				WO2⁽²⁾		EVOUTF	3, IN2
23	-	-	-	-	-	PF3		AIN19		X35/Y35							3, OUT
24	-	-	-	-	-	PF4		AIN20		X36/Y36					0, WO⁽²⁾
25	-	-	-	-	-	PF5		AIN21		X37/Y37					1, WO⁽²⁾
26	22	18	15	2	2	PF6⁽⁵⁾	RESET				RxD⁽²⁾
27	23	19	16	3	3	PF7	UPDI			X39/Y39	TxD⁽²⁾	SS⁽²⁾				EVOUTF⁽²⁾
28	24	20	-	-	-	VDD
29	25	21	-	-	-	GND

Note:

The pin names are of the Pxn type, where x denotes the PORT instance (A, B, C, ...) and n denotes the pin number. The notation for signals is PORTx_PINn. All pins can be used as event inputs.
Alternative pin positions. For selecting alternate positions, refer to the PORTMUX - Port Multiplexer chapter.
The TWI pins that can be used as host or client pins are marked “HC”, while pins marked “C” can only be used as client pins.
External Integration capacitor pins for the PTC.
Input-only.