1 Theory of Operation

Before the XMEGA watchdog timer can be discussed, it is important to get a few terms clear:

• The Watchdog Timer (WDT) is the peripheral module that can be configured to generate a system Reset, if the timer is Reset too early or too late according to specified timeout periods. The timer value itself cannot be read or written, only Reset.
• A Watchdog Timer Reset (WDT Reset) is when the timer in the WDT is cleared (or Reset). This will make the timer start counting from zero again, and thus restart the timeout period.
• A system Reset is when the AVR microcontroller is Reset, resetting the CPU and I/O register to default values and restarting program execution from address 0x0000 (or boot section). The WDT can cause a system Reset if it times out or, in Window mode, if the WDT is Reset too early.