1.3.6 Bus Time-Out Causes False Start/Stop
When the module is operating in Client mode and an external Host device is clock stretching and a bus time-out occurs in the Client, the Client releases SDA and goes into the idle state. After the external Host generates a Stop condition on the bus by releasing SCL, the module can erroneously drive a low pulse on the SDA line, which acts as a false Start and Stop on the bus.
Work around
None.
Affected Silicon Revisions
| A4 | A5 | A6 | B1 |
| X | X | X | X |