The PIC18F06/16Q40 devices you have received conform functionally to the current device data sheet (DS40002216D), except for the anomalies described in this document.

The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in the table below.

The errata described in this document will be addressed in future revisions of the PIC18F06/16Q40 silicon.

Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current.
Table . Silicon Device Identification
Part Number Device ID Revision ID
A4 A5 A6 B1
PIC18F06Q40 0x75C0 0xA004 0xA005 0xA006 0xA041
PIC18F16Q40 0x75A0 0xA004 0xA005 0xA006 0xA041
Important: Refer to the Device/Revision ID section in the current “PIC18-Q40 Family Programming Specification” (DS40002185) for more detailed information on Device Identification and Revision IDs for your specific device.
Table . Silicon Issue Summary
Module Feature Item No. Issue Summary Affected Revisions
A4 A5 A6 B1
Analog-to-Digital Converter with Computation ADCC 1.1.1  ADC cannot operate in certain low-power conditions X
1.1.2  Double Sample Conversions X X X
Oscillator XT mode 1.2.1  Maximum clock frequency limited to 2 MHz for XT mode X
Fail-Safe Clock Monitor 1.2.2  Enabling the FOSC Fail-Safe Clock Monitor alongside the Primary or Secondary Oscillator Clock Monitor causes issues in Sleep X
EC mode 1.2.3  Maximum clock frequency for EC mode is 32 MHz for VDD < 2.0V X
I2C I2C 1.3.1  I2CxADR0/1/2/3 registers have incorrect Reset value X
1.3.2  I2C Start and/or Stop Flags May be set when I2C is Enabled X X
1.3.3  MDR bit is not cleared after Bus Time-out X X X X
1.3.4  Bus Time-out not detected properly when External Host Clock stretches X X X X
1.3.5  Clock Stretch Disable not working properly X X X X
1.3.6  Bus Time-out causes false Start/Stop X X X X
1.3.7  CSTR bit is not cleared after bus time-out X X X X
Multi-Host Mode 1.3.8  Operating in Multi-Host Mode will cause bus failures X X X X
Universal Asynchronous Receiver Transmitter UART 1.4.1  UART TXDE signal may go low before the STOP bit has been entirely transmitted X X X
1.4.2  Asynchronous 9-bit UART Address Mode Address Mismatch X X X
Signal Measurement TImer SMT 1.5.1  Reset Bit X X X
PIC18 CPU FSR Shadow Registers 1.6.1  FSR Shadow Registers are not writable X X X
ICSP™ Low-Voltage Programming (LVP) 1.7.1  Low Voltage Programming is not possible when VDD is below BORV while BOR is enabled X X X
Note: Only those issues indicated in the last column apply to the current silicon revision.