3.2.2.1 Connectors

The PL360G55CF-EK board includes the following connectors:

1. PLC connector (for an AC/DC grid), J1.

   Table 3-1. PLC Connector (for an AC/DC grid), J1

   Pin	Signal Name	Description
   1	L / +VDC	Line / Positive Voltage
   2	N / -VDC	Neutral / Negative Voltage

2. Micro-B female USB connector, J4.

   Table 3-2. USB Device Connector, J4

   Pin	Signal Name	Description
   1	VUSB	5V power
   2	D+	Data Plus
   3	D-	Data Minus
   4	ID	On the Go Identification
   5	GND	Ground

3. mikroBUS add-on connectors, J5 and J6.

   Table 3-3. mikroBUS Connector, J5

   Pin	Mnemonic	Description
   1	AN	Analog
   2	RST	Reset
   3	CS	SPI Chip Select
   4	SCK	SPI Clock
   5	SDO	SPI Master Input Slave Output
   6	SDI	SPI Master Output Slave Input
   7	3V3	VCC - 3.3V power
   8	GND	Reference Ground

   Table 3-4. mikroBUS Connector, J6

   Pin	Mnemonic	Description
   1	PWM	PWM
   2	INT	Hardware Interrupt
   3	TX	UART Transmit
   4	RX	UART Receive
   5	SCL	I2C Clock
   6	SDA	I2C Data
   7	5V	VCC - 5V power
   8	GND	Reference Ground

4. JTAG/SWD 10-pin connector for SAMG55J19, J7.

   Table 3-5. SW-DP Connector, J7

   Pin	Mnemonic	Description
   1	VCC	This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input comparators, and to control the output logic levels to the target. It is normally fed from VCC on the target board and must not have a series resistor.
   2	SWDIO/TMS	Serial Wire Input Output / Test Mode Select. JTAG mode set input of target CPU. This pin should be pulled up on the target. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal.
   3	GND	Ground.
   4	SWDCLK/TCK	Serial Wire Clock / Test Clock. JTAG clock signal to target CPU (output timing signal, for synchronizing test logic and control register access).
   5	GND	Ground.
   6	SWO/TDO	Test Asynchronous Data Out from target CPU.
   7	KEY	-
   8	NC/TDI	Not Connected / Test Data Input. JTAG data input of target CPU (serial data output line, sampled on the rising edge of the TCK signal). It is recommended that this pin is pulled to a defined state on the target board.
   9	GND Detect	Ground.
   10	nRESET	JTAG Reset (active-low output signal that resets the target). Output from SAM-ICE™ to the Reset signal on the target JTAG port. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.

5. DC Input connector, J8.

   Table 3-6. DC Input Connector, J8

   Pin	Signal Name	Description
   1	DC_IN	DC Input voltage (6 - 30V)
   2	GND	Ground
   3	-	-