1.2 NAND Flash Organization

The NAND Flash array is organized as a series of blocks divided into several pages. Data is stored either in a byte (8 bits) or half-word (16 bits) format, depending on the device type. Each page consists of a main area for storing data and a spare area (physically similar), typically used for data error identification and correction, wear leveling, etc.

One particularity of NAND Flash devices is that they may contain a percentage of invalid blocks in the memory array. The NAND Flash manufacturer identifies and marks the bad blocks as "Invalid blocks". This information is stored in the spare area of the first or second page of the block. The existence of bad blocks does not affect the other blocks because each one is independent and individually isolated from the bit lines by block select transistors.

As NAND Flash devices have a finite lifetime (approximately 60 K to 100 K erase/write cycles for SLC and 3 K to 5 K erase/write cycles for MLC), additional invalid blocks may develop while being used. Storing data requires bad block management and data error identification and correction.