2.1 Pin Details of WILCS02IC

This section provides details on pin diagrams and the pinout table of WILCS02IC.

Table 2-1. WILCS02IC Pinout Table
Pin Number	Pin Name	Pin Type	Description
1	PMU_VDDIO/ PMU_VDDC	P	Input power supply to the on-chip PMU I/O and PMU Core section (3.0-3.6V, 3.3V typical)
2	VDD15	P	1.5V input supply voltage Connect to 1.5V on-chip PMU output
3	SD_CMD/SCK1	I	SDIO, Command Connect to the SDIO command of the host device
3	SD_CMD/SCK1	I	SPI1, Serial Clock Connect to the SPI Clock of the host device
4	SD_CLK/UART1_RX⁽⁵⁾	I	SDIO, Clock Connect to the SDIO clock of the host device
4	SD_CLK/UART1_RX⁽⁵⁾	I	Used for external antenna calibration Connect this signal to a test point or a pin header
5	SD_DATA0/SDO1	I/O	SDIO, Data0 Connect to the SDIO data0 of the host device
5	SD_DATA0/SDO1	O	SPI1, Serial Data Out Connect to the Serial Data In of the host device
6	SD_DATA1/CS1	I/O	SDIO Data 1 Connect to the SDIO data1 of the host device
6	SD_DATA1/CS1	I	SPI1 Chip Select (Active-low) Connect to the Chip Select of the host device
7	VDDIO	P	Input supply voltage to I/O Port (3.0-3.6V, 3.3V typical)
8	SD_DATA2/SDI1	I	SDIO, Data 2 Connect to the SDIO data2 of the host device
8	SD_DATA2/SDI1	I	SPI1, Serial Data In Connect to Serial Data Out of the host device
9	SD_DATA3/UART1_TX⁽⁵⁾	I/O	SDIO Data 3 Connect to the SDIO data3 of the host device
9	SD_DATA3/UART1_TX⁽⁵⁾	O	Used for external antenna calibration Connect this signal to a test point or a pin header
10	INTOUT	O	Interrupt request (Active-low) from the Wi-Fi® device
11	UART2_TX	O	UART2 Transmit signal to print the firmware debug log
12	Reserved	I/O	Reserved pin, do not connect
13	Reserved	I/O	Reserved pin, do not connect
14	VDD33	P	Input supply voltage for the Main Power Domain (3.0-3.6V, 3.3V typical)
15	SPI_VDD15	P	1.5V input supply voltage to the RF internal SPI logic block Connect to 1.5V on-chip PMU output
16	AFE_VDD15	P	1.5V input supply voltage to RF Analog Front-End Connect to 1.5V on-chip PMU output
17	XTL_VDD15	P	1.5V input supply voltage to primary oscillator section Connect to 1.5V on-chip PMU output
18	XTL_IN	I	40 MHz primary oscillator crystal input
19	XTL_OUT	O	40 MHz primary oscillator crystal output
20	SYN_SD_VDD15	P	1.5V input supply voltage to RF Synthesizer/SD Connect to 1.5V on-chip PMU output
21	SYN_PLL_VDD15	P	1.5V Input supply voltage to RF Synthesizer/PLL Connect to 1.5V on-chip PMU output
22	SYN_VCO_VDD15	P	1.5V input supply voltage to RF Synthesizer/VCO Connect to 1.5V on-chip PMU output
23	SPI_FE_VDD15	P	1.5V input supply voltage to the RFIP Front-End and internal SPI logic block Connect to 1.5V on-chip PMU output
24	RXR_RIQ_VDD15	P	1.5V input supply voltage to RF IQ Mixer/RXR Connect to 1.5V on-chip PMU output
25	RXR_LNA2_VDD15	P	1.5V input supply voltage to LNA stage-2 Connect to 1.5V on-chip PMU output
26	RXR_LNA1_VDD15	P	1.5V input supply voltage to LNA stage-1 Connect to 1.5V on-chip PMU output
27	TRS_RF	I/O	RF transmit/receive
28	TXR_HPA_VDD33	P	Input power supply to High-Power Amplifier (HPA) on the Transmitter (3.0-3.6V, 3.3V typical)
29	TXR_HPA_VDD33	P
30	TXR_PPA_VDD33	P	Input power supply to Pre-Power Amplifier (PPA) on the Transmitter (3.0-3.6V, 3.3V typical)
31	TXR_UMX_VDD15	P	1.5V input supply voltage to RF Upconvertor Mixer/TXR Connect to 1.5V on-chip PMU output
32	BB_VDD15	P	1.5V input supply voltage to RF Base Band section Connect to 1.5V on-chip PMU output
33	MSB_EXTRA_48K	O	RF calibration resistor, connect a pull-down resistor of 48.7K with 1% tolerance
34	DFU_RX/STRAP1	I/O	Device Firmware Update, receive signal
34	DFU_RX/STRAP1	I/O	Host interface configuration strapping1 pin. Connect to a pulled-low resistor of 100K for the SDIO interface or pulled-high resistor of 10K for the SPI.
35	DFU_TX/STRAP2	I/O	Device Firmware Update, transmit signal
35	DFU_TX/STRAP2	I/O	Host interface configuration strapping2 pin. Connect to a pulled-high resistor of 10K for future upgrades.
36	MCLR	I	Master Clear Reset Input (Active low)
37	AVDD	P	Input power supply to Analog Block (3.0-3.6V, 3.3V typical)
38	Reserved⁽⁶⁾	I/O	Reserved pin Connect to an I/O pin (tri-stated) of a host device or to an external switch for future use.
39	RTCC_OSC_OUT⁽⁴⁾	O	32.768 KHz RTCC oscillator output
40	RTCC_OSC_IN/PTA_BT_ACTIVE⁽³⁾⁽⁴⁾	I	32.768 KHz RTCC Oscillator input
40	RTCC_OSC_IN/PTA_BT_ACTIVE⁽³⁾⁽⁴⁾	I	PTA interface, Bluetooth® Coexistence device active indication input to WILCS02IC
41	VDD33	P	Input supply voltage for the Main Power Domain (3.0-3.6V, 3.3V typical)
42	PTA_BT_PRIO	I	PTA interface, Bluetooth Coexistence device priority indication input to WILCS02IC.
43	PTA_WLAN_ACTIVE	O	PTA interface, WILCS02IC WLAN active indication output to Bluetooth Coexistence device
44	Reserved	I/O	Reserved pin Do not connect.
45	VDD33	P	Input supply voltage for the Main Power Domain (3.0-3.6V, 3.3V typical)
46	PMU_MLDO_OUT⁽²⁾	P	1.5V output of on-chip PMU MLDO
47	PMU_VDDP	P	Input power supply to the on-chip PMU (3.0-3.6V, 3.3V typical)
48	PMU_BK_LX	P	1.5V output of on-chip PMU Buck Regulator Connect to an external LC filter (L = 4.7 uH and C = 10 uF)
49	GND	P	Thermal ground paddle
Note: Refer to the reference design package for exact pin mapping and signal connection. Do not connect any signal to source the voltage as this is for internal purposes only. The WILCS02IC can support either RTCC_OSC_IN or PTA_BT_ACTIVE functionality at a time, so either RTCC or PTA feature can be used. Current firmware does not support the Real Time Clock Calendar (RTCC) Oscillator function; it is recommended to have an option to mount the RTCC Oscillator in the design to upgrade with the future version of firmware releases. For more details, refer to the WILCS02 Module External Antenna Calibration Guide (DS50003751). Do not leave this pin unconnected. Follow as described in the Pin Description column for future upgrade.