1.3 SPI Peripheral Handling

To perform the accesses to serial memory the SPI interface: a synchronous serial communication interface is used.

During each SPI clock cycle, the master sends a bit on the MOSI line and the slave reads it, while the slave sends a bit on the MISO line and the master reads it. This sequence is maintained even when only one-directional data transfer is intended.

The SPI operates byte-wise. After a byte was sent or received, the flag SPIF is set in the INTFLAGS register.

There are two possible methods of SPI peripheral operation:

1. Polling the INTFLAGS register to detect if the SPIF was set, and then perform the next SPI transfer.
2. Enable the SPI interrupt and manage the next SPI transfer in the SPI interrupt handler.