23.7.4 Clock Divider Control n Register

Table 23-6. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	CLKDIV
Offset:	0x0C + n*0x04 [n=0..2]
Reset:	0x00000001
Property:	R/W


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8

Access
Reset


Bit	7	6	5	4	3	2	1	0
	DIV[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	1

Bits 7:0 – DIV[7:0] Division Ratio

These bits define the division ratio of the main clock prescaler related to the Clock Domain controlled by the CLKDIVn register. To ensure correct operation, frequencies must be selected so that FCLKDIV[n]≥ FCLKDIV[n+1] (i.e. CLKDIVn.DIV ≤ CLKDIV(n+1).DIV).

Frequencies must never exceed the specified maximum frequency for each clock domain. An update to this register may not take affect immediately. The MCLK peripheral will wait for the falling edge of the previous clock and the new clock to coincide before switching. The INTFLAG.CKRDY can be used to determine when MCLK has made the switch.

Note: All other values are reserved or invalid.

Value	Name	Description
1	DIV1	Divide by 1
2	DIV2	Divide by 2
4	DIV4	Divide by 4
8	DIV8	Divide by 8
16	DIV16	Divide by 16
32	DIV32	Divide by 32
64	DIV64	Divide by 64
128	DIV128	Divide by 128