Jump to main content
23.7.5 Peripheral Clock Enable Mask n Register
Table 23-7. Register Bit Attribute Legend Symbol Description Symbol Description Symbol Description R Readable bit HC Cleared by Hardware (Grey cell) Unimplemented W Writable bit HS Set by Hardware X Bit is unknown at Reset K Write to clear S Software settable bit — —
Name: CLKMSK Offset: 0x3C + n*0x04 [n=0..2] Reset: 0x00000000 Property: R/W
Bit 31 30 29 28 27 26 25 24 MASK31 MASK30 MASK29 MASK28 MASK27 MASK26 MASK25 MASK24 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16 MASK23 MASK22 MASK21 MASK20 MASK19 MASK18 MASK17 MASK16 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 MASK15 MASK14 MASK13 MASK12 MASK11 MASK10 MASK9 MASK8 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 MASK7 MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0 Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – MASK Peripheral
Clock Mask bit Value Description 0 Peripheral
clock stopped 1 Peripheral
clock enabled
On this page
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – MASK Peripheral
Clock Mask bit
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
