39.15.3 LUT Control x

Note: LUTCTRLn register is Enable Protected when CCL.LUTCTRLn.ENABLE = 1.

Table 39-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	LUTCTRL
Offset:	0x08 + n*0x04 [n=0..3]
Reset:	0x00000000
Property:	PAC Write-Protection, Enable-protected


Bit	31	30	29	28	27	26	25	24
	TRUTH[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
		LUTEO	LUTEI	INVEI	INSEL2[3:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	INSEL1[3:0]				INSEL0[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	EDGESEL		FILTSEL[1:0]				ENABLE
Access	R/W		R/W	R/W			R/W
Reset	0		0	0			0

Bits 31:24 – TRUTH[7:0] Truth Value

These bits define the value of truth logic as a function of inputs IN[2:0].

Bit 22 – LUTEO LUT Event Output Enable

Value	Name	Description
0	DISABLE	LUT event output is disabled
1	ENABLE	LUT event output is enabled

Bit 21 – LUTEI LUT Event Input Enable

Value	Name	Description
0	DISABLE	LUT incoming event is disabled
1	ENABLE	LUT incoming event is enabled

Bit 20 – INVEI Inverted Event Input Enable

Value	Name	Description
0	NORMAL	Incoming event is not inverted
1	INVERTED	Incoming event is inverted

Bits 8:11, 12:15, 16:19 – INSELx LUTn Input Source Selection [n=0..2]

These bits select the LUTn input source for CCLm:

Table 39-8. CCL Internal Connection
	0x4	0x5	0x6	0x7	0x8	0x9	0xA
LUT0.IN0	CCLm_IN0	AC0 output	SERCOM0 padout[0]	TCC0 WO0	TCC0 WO4	TCC4 WO0	TCC5 WO0
LUT0.IN1	CCLm_IN1	AC0 output	SERCOM0 padout[0]	TCC0 WO1	TCC0 WO5	TCC4 WO1	TCC5 WO1
LUT0.IN2	CCLm_IN2	AC0 output	SERCOM0 padout[0]	RESERVED	TCC0 WO6	TCC4 WO0	TCC5 WO0
LUT1.IN0	CCLm_IN3	AC1 output	SERCOM1 padout[0]	TCC1 WO0	RESERVED	TCC6 WO0	RESERVED
LUT1.IN1	CCLm_IN4	AC1 output	SERCOM1 padout[0]	TCC1 WO1	RESERVED	TCC6 WO1	RESERVED
LUT1.IN2	CCLm_IN5	AC1 output	SERCOM1 padout[0]	RESERVED	RESERVED	TCC6 WO0	RESERVED
LUT2.IN0	CCLm_IN6	AC0 output	SERCOM2 padout[0]	TCC2 WO0	RESERVED	TCC0 WO0	TCC1 WO0
LUT2.IN1	CCLm_IN7	AC0 output	SERCOM2 padout[0]	TCC2 WO1	RESERVED	TCC0 WO1	TCC1 WO1
LUT2.IN2	CCLm_IN8	AC0 output	SERCOM2 padout[0]	RESERVED	RESERVED	TCC0 WO0	TCC1 WO0
LUT3.IN0	CCLm_IN9	AC1 output	SERCOM3 padout[0]	TCC3 WO0	RESERVED	TCC2 WO0	TCC3 WO0
LUT3.IN1	CCLm_IN10	AC1 output	SERCOM3 padout[0]	TCC3 WO1	RESERVED	TCC2 WO1	TCC3 WO1
LUT3.IN2	CCLm_IN11	AC1 output	SERCOM3 padout[0]	RESERVED	RESERVED	TCC2 WO0	TCC3 WO0

Value	Name	Description
0x0	MASK	Masked input
0x1	FEEDBACK	Feedback input source
0x2	LINK	Linked LUT input source
0x3	EVENT	Event input source
0x4	IO	I/O pin input source
0x5	AC	AC input source
0x6	SERCOM	SERCOM input source
0x7	TCC	TCC input source
0x8	TCC	TCC input source
0x9	TCC	TCC input source
0xA	TCC	TCC input source
0xB - 0xF	Reserved	Reserved

Bit 7 – EDGESEL Edge Selection

Value	Name	Description
0	DISABLE	Edge detector is disabled
1	ENABLE	Edge detector is enabled

Bits 5:4 – FILTSEL[1:0] Filter Selection

These bits select the LUT output filter options:

Filter Selection

Value	Name	Description
0	DISABLE	Filter disabled
1	SYNCH	Synchronizer enabled
2	FILTER	Filter enabled

Bit 1 – ENABLE LUT Enable

Value	Name	Description
0	DISABLE	LUT block is disabled
1	ENABLE	LUT block is enabled

DS60001921A

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