37.5.3 Timeout Counter

To signal timeout conditions for Rx FIFO 0, Rx FIFO 1, and the Tx Event FIFO the CAN supplies a 16-bit Timeout Counter. It operates as down-counter and uses the same prescaler controlled by the TSCC.TCP bit (TSCC <19:16>) as the Timestamp Counter. The Timeout Counter is configured through the TOCC register. The actual counter value can be read from the TOCV.TOC bits (TOCV <15:0>). The Timeout Counter can only be started while the CCCR.INIT bit (CCCR <0>) = 0. It is stopped when the CCCR.INIT bit (CCCR <0>) = 1, for example, when the CAN enters 'bus off' state.

The operation mode is selected by the TOCC.TOS bits (TOCC <2:1>). When operating in continuous mode, the counter starts when the CCCR.INIT bit (CCCR <0>) is reset. A write to TOCV presets the counter to the value configured by the TOCC.TOP bits (TOCC <31:16>) and continues down-counting.

When the Timeout Counter is controlled by one of the FIFOs, an empty FIFO presets the counter to the value configured by the TOCC.TOP bits (TOCC <31:16>). Down-counting is started when the first FIFO element is stored. Writing to TOCV has no effect.

When the counter reaches zero, the Interrupt Flag, IR.TOO bit ( IR<18>) is set. In continuous mode, the counter is immediately restarted at the TOCC.TOP bits (TOCC <31:16>).

Note: The clock signal for the Timeout Counter is derived from the CAN Core’s sample point signal. Therefore the point in time where the Timeout Counter is decremented may vary due to the synchronization/re-synchronization mechanism of the CAN Core. If the baud rate switch feature in CAN FD is used, the timeout counter is clocked differently in arbitration and data field.