28.4 Block Transfer Destination Address
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | DSTADDR |
| Offset: | 0x08 |
| Reset: | None |
| Property: | RW |
The DSTADDR register offset is relative to (BASEADDR or WRBADDR) + Channel Number * 0x10
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| DSTADDR[31:24] | |||||||||
| Access | |||||||||
| Reset | |||||||||
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| DSTADDR[23:16] | |||||||||
| Access | |||||||||
| Reset | |||||||||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| DSTADDR[15:8] | |||||||||
| Access | |||||||||
| Reset | |||||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DSTADDR[7:0] | |||||||||
| Access | |||||||||
| Reset | |||||||||
Bits 31:0 – DSTADDR[31:0] Transfer Destination Address
This bit group holds the destination address corresponding to the last beat transfer address in the block transfer.