40.2 Features

The Multi-Shared-Channel digital Controller in conjunction with the Microchip Internal Analog ADC SAR core implements these features:

• Up to 12-bit resolution of the numerical output, signed or unsigned
• Signed outputs left-adjusted or right-adjusted
• Up to 4.5 Msps conversion rate per channel
• Up to 16 analog inputs.
• Single-ended and/or differential-ended inputs on a per channel basis for all channels.
• Up to 16 trigger sources, off-chip hardware or on-chip hardware or software generated
• Edge or level active triggering modes, to generate single conversions or bursts of conversions
• A scan trigger per each shared Analog ADC SAR Core to start a scan cycle which can individually include, or not, any of the analog inputs assigned to that Analog ADC SAR Core
• Any channel can select any of the 16 trigger sources or the scan trigger as its own trigger sources or the scan trigger as its own trigger
• The scan trigger itself can select any of the 16 trigger sources as its own source
• Programmable sampling time per Analog ADC SAR Core
• Each Analog Input or Channel Output register can be read from a general dedicated APB output register (user writes the CORDYID and CHRDYID then reads the CHRDYDATA register)
• Optional FIFO-buffered OCP-based DMA Bus Mastering Interface for all channels (Open Core Protocol (OCP))
• APB-accessible FIFO for all channels (intended for systems without the DMA bus mastering interface option). Intended to be used with the system DMA.
• 1 Digital Comparators for monitoring output values in relation to user-specified thresholds; there can be at most one digital comparator assigned to each Analog ADC Core, because only one channel per Analog ADC Core can be converted at a time
• 1 Digital filters they provide averaging for increased noise immunity and are assignable to any analog input; there can be at most one digital filter assigned to each Analog ADC Core, because only one channel per Analog ADC Core can be converted at a time.