36.6.4.2.3 Clock and Clock Generation

Clock

The SERCOM bus clock (CLK_SERCOMx_APB) can be enabled and disabled in the Device Main Clock Controller. Refer to Peripheral Clock Masking for details and default status of this clock.

A generic clock (GCLK_SERCOMx_CORE) is required to clock the SPI. This clock must be configured and enabled in the Device Generic Clock Controller before using the SPI.

Note: GCLK_SERCOMn_CORE is the only clock the user should select for the SERCOM in SPI mode.

This generic clock is asynchronous to the bus clock (CLK_SERCOMx_APB). Therefore, writing to certain registers will require synchronization between the clock domains. Refer to Synchronization for further details.

Clock Generation

In SPI host operation (CTRLA.MODE = 0x3), the serial clock (SCK) is generated internally by the SERCOM Baud Rate Generator.

In SPI mode, the Baud Rate Generator is set to synchronous mode. The 8-bit Baud register (BAUD) value is used for generating SCK and clocking the Shift register. Refer to Clock Generation – Baud-Rate Generator for more details.

In SPI client operation (CTRLAS.MODE is 0x2), the clock is provided by an external host on the SCK pin. This clock is used to directly clock the SPI Shift register.