37.2 Tx Buffer Element 1

Table 37-89. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Grey cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
K	Write to clear	S	Software settable bit	—	—

Name:	T1
Offset:	0x004
Reset:	0x00000000
Property:	-


Bit	31	30	29	28	27	26	25	24
	MML[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	EFC	TSCE	FDF	BRS	DLC[3:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	MMH[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0

Access
Reset

Bits 31:24 – MML[7:0] Message Marker Lower Byte

Written by CPU during Tx Buffer configuration. Copied into Tx Event FIFO element for identification of Tx message status.

Bit 23 – EFC Event FIFO Control

Value	Description
0	Don’t store Tx events.
1	Store Tx events.

Bit 22 – TSCE Time Stamp Capture Enable for TSU

Bit 21 – FDF FD Format

Value	Description
0	Frame transmitted in Classic CAN format.
1	Frame transmitted in CAN FD format.

Bit 20 – BRS Bit Rate Search

Note: Bits ESI, FDF, and BRS are only evaluated when CAN FD operation is enabled CCCR.FDOE = ‘1’. Bit BRS is only evaluated when in addition CCCR.BRSE = ‘1’.

Value	Description
0	CAN FD frames transmitted without bit rate switching.
1	CAN FD frames transmitted with bit rate switching.

Bits 19:16 – DLC[3:0] Identifier

Value	Description
0-8	CAN + CAN FD: received frame has 0-8 data bytes
9-15	CAN: received frame has 8 data bytes.
9-15	CAN FD: received frame has 12/16/20/24/32/48/64 data bytes

Bits 15:8 – MMH[7:0] Message Marker Higher Byte

DS60001921A

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