20.1.2 Synchronous and Asynchronous Clocks

As the CPU and the peripherals can be in different clock domains, peripheral accesses by the CPU need to be synchronized. In this case the peripheral includes a Synchronization Busy (SYNCBUSY) register that can be used to check if a sync operation is in progress.

Synchronous Clocks are generated by the CPU and bus clocks Main Clock Controller (MCLK), while asynchronous clocks are generated by the Generic Clock Controller (GCLK).