36.11.6 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear register (INTENCLR). On read, a bit value of zero indicates the associated interrupt is disabled while a bit value of one indicates the associated interrupt is enabled.
Table 36-56. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit——
Name: INTENSET
Offset: 0x16
Reset: 0x00
Property: RW

Bit 76543210 
 ERROR  RXFFTXFE SBMB 
Access R/WR/WR/WR/WR/W 
Reset 00000 

Bit 7 – ERROR Combined Error Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Error Interrupt Enable bit, which enables the Error interrupt.

Bit 4 – RXFF Rx FIFO Full Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the RX FIFO Full bit, which enables the RX FIFO Full interrupt.

ValueDescription
0The RX FIFO Full interrupt is disabled.
1The RX FIFO Full interrupt is enabled.

Bit 3 – TXFE Tx FIFO Empty Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the TX FIFO Empty bit, which enables the TX FIFO Empty interrupt.

ValueDescription
0The TX FIFO Empty interrupt is disabled.
1The TX FIFO Empty interrupt is enabled.

Bit 1 – SB Client On Bus Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Client on Bus Interrupt Enable bit, which enables the Client on Bus interrupt.

ValueDescription
0The Client on Bus interrupt is disabled.
1The Client on Bus interrupt is enabled.

Bit 0 – MB Host On Bus Interrupt Enable

Writing '0' to this bit has no effect.

Writing '1' to this bit will set the Host on Bus Interrupt Enable bit, which enables the Host on Bus interrupt.

ValueDescription
0The Host on Bus interrupt is disabled.
1The Host on Bus interrupt is enabled.