Important: This register is only present in devices with security attribution.
This
register allows the user to disable an interrupt without doing a read-modify-write
operation. Changes in this register will also be reflected in the Interrupt Enable Clear
register (INTENCLR).
Table 35-23. Register Bit Attribute Legend
Symbol
Description
Symbol
Description
Symbol
Description
R
Readable bit
HC
Cleared by Hardware
(Grey cell)
Unimplemented
W
Writable bit
HS
Set by Hardware
X
Bit is unknown at Reset
K
Write to clear
S
Software settable bit
—
—
Name:
INTENSET
Offset:
0x64
Reset:
0x00000000
Property:
PAC
Write-Protection
Bit
31
30
29
28
27
26
25
24
Access
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
Access
Reset
Bit
7
6
5
4
3
2
1
0
Access
Reset
DS60001921A
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.
