1 References

For information about transceiver clock regions, see PolarFire Family Transceiver User Guide.
For information about I/O interface modes and high-speed I/O clock networks, see PolarFire Family I/O User Guide.
For information about device power-up, see PolarFire Family Device Power-Up and Resets User Guide.
For information about the performance of the global clock for the transceiver quads, minimum setup and hold time for the clock gating enable signal, electrical characteristics of the on-chip oscillators, and PLL jitter performance, see the respective PolarFire FPGA Datasheet , RT PolarFire FPGA Datasheet , PolarFire SoC FPGA Datasheet , or RT PolarFire SoC FPGA Datasheet
For information about using Libero® SoC for PolarFire FPGA and PolarFire SoC FPGA, see Libero SoC Documentation.
For information about MSS, see PolarFire SoC FPGA MSS Technical Reference Manual.