5 MSS Clock Controller (For PolarFire SoC and RT PolarFire SoC FPGA Only)

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The PolarFire SoC and RT PolarFire SoC MSS have a dedicated clock controller for generating clocks to all the MSS sub-blocks for correct operation and synchronous communication with the user logic in the FPGA fabric. The MSS clock controller includes dedicated PLLs (MPLLs, DDR PLL, and SGMII PLL) for MSS clocking. The base clock for these PLLs comes either from a dedicated I/O (REFCLK) from Bank5 or one of the NW PLL outputs—OUT2 or OUT3. This dedicated I/O can be connected to a clock source, which can supply a 100 MHz or 125 MHz clock.

For MSS PLL radiation test results, refer to the Radiation Test Reports on the Microchip website (for example, the PolarFire SoC MSS Heavy Ion Test Results).