6 Revision History

• Updated the document for RT PolarFire® SoC support. The changes are made throughout the document.
• Updated the descriptions of DELAY_LINE_ DIRECTION and DELAY_LINE_WIDE ports in Table 4-1.

• Removed the following sentence from Global Clock Network: The skew is guaranteed to be less than the shortest possible propagation delay.
• Added information about lock signal assertion and de-assertion in the Lock Output section.
• Updated Figure 2-1 and Figure 4-2 by removing the arrow going from the Transceiver block to CCC NE for indicating that the Transceiver block can drive clock to CCC SE and not to CCC NE.
• Added a note about the simulation support limitation in the CCC Simulation Support section.

• Added a note about the unused condition of the on-chip oscillators in the On-Chip Oscillators section.
• Added information about the radiation test reports which must be used to decide the CCC PLL usage in RT PolarFire devices. See the Phase-Locked Loops section.
• Added a precautionary note in the Clock Frequency Synthesis section.

• Updated the document title and added RT PolarFire information.
• Updated information about PLL_POWERDOWN_B control of CCC when using feedback modes. See Power-Down Input, Internal Post-Divider Feedback Mode, and External Feedback Mode.

• Updated note about static phase shift in post-divider and external feedback modes. See Static Phase Shifting.
• Added a note about post-VCO mode and post-divider mode. See Dynamic Phase Shifting.
• Updated information about integer mode, See CCC Configuration.

• Added information about Global clock networks susceptible to clock jitter. See Global Net Clock Jitter.
• Added a note about clock jitter constraints. See Managing Global Signals and Clock Outputs.

This user guide was created by merging the following documents:

• UG0684: PolarFire FPGA Clocking Resources User Guide
• UG0913: PolarFire SoC FPGA Clocking Resources User Guide

• Information about CCC Configuration was updated.
• Changed PSTRB signal from low to high. See CCC Dynamic Configuration System figure.
• Information about BYPASS_EN_N was removed.

• Information about External Feedback Mode was updated.
• Information about CCC Configuration was updated.
• Information about Dynamic Phase Shifting was updated.
• Information about Preferred Clock Inputs Connectivity in CCCs was updated.

• Information about performance of global clock for the transceiver quads was removed and referred to PolarFire FPGA Datasheet.
• Information about Requested Phase field of CCC configurator was added. See CCC Configuration.
• Information about PLL Reference Clock Inputs was updated. See Reference Clock Inputs.
• Information about RC Oscillators Configurator Ports was added.
• Information about Reference Clock Inputs was updated.
• Information related to Libero SoC v12.1 was updated.

• Information about PLL reference clock was added. See Reference Clock Inputs.
• Port names were matched according to Libero SoC PolarFire v2.3.
• Information about Internal Post-VCO Feedback Mode, Internal Post-Divider Feedback Mode, and External Feedback Mode was updated.

• Information about interface clock block was added. See Interface Clock Block.
• Information about global clock networks was updated. See Global Clock Network.
• Information about CCC_SW_CLKIN_W<3:0> was added.
• Information about BIT_SLIP signal was added. See Clock Dividers.
• Information about bandwidth adjustment was updated. See PLL Bandwidth Parameter Settings table.

• Information about global clock networks was updated.
• The document was updated to include features and enhancements introduced in the Libero SoC PolarFire v2.0 release.

The following is a summary of the changes made in this revision:

• Information about PLL/DLL Placement was added. See PLL/DLL Placement.
• Global Clock Network and Clock Sources figure, and System-Level Block Diagram of CCCs figure were updated.

• Information about Preferred Clock Inputs Connectivity in CCCs was updated.
• Information about Glitch-Free Clock Switching was updated.

• Information about CCC Configuration was updated.
• Changed PSTRB signal from low to high. See CCC Dynamic Configuration System figure.
• Information about BYPASS_EN_N was removed.