1.1 Clock Routing Resources

To enable efficient clock distribution, the PolarFire family has a global clock network, regional clock networks, high-speed I/O clock networks, and preferred clock inputs and outputs.

• Global Clock Network is used to distribute high fan-out signals, such as clocks and resets across the FPGA fabric with low skew.
• Regional Clock Networks are low-latency networks that distribute clocks only to a specific designated area based on the driving source. Regional clock networks are used to move data in and out of the fabric.
• High-Speed I/O Clock Networks are used to distribute high-speed clocks along the edge of the device to service the I/Os. High-speed I/O clock networks are used to implement high-speed interfaces.
• Preferred Clock Inputs have access to the global clock network and/or CCCs through low-latency paths. Preferred clock input pins are recommended for connecting external clocks to the clock inputs of Phase-Locked Loops (PLLs), Delay-Locked Loops (DLLs), and fabric logic. While it is possible to use regular I/Os as clock inputs, doing so introduces high latency on the path.
• Preferred Clock Outputs are used to connect PLL clock outputs to external components. Preferred clock output pins have low-latency routing from the PLL clock outputs.