PIC16(L)F18424/44

32.8.18 ADCON3

ADC Control Register 3

Name:	ADCON3
Offset:	0x114


Bit	7	6	5	4	3	2	1	0
		CALC[2:0]			SOI	TMD[2:0]
Access		R/W	R/W	R/W	R/W/HC	R/W	R/W	R/W
Reset		0	0	0	0	0	0	0

Bits 6:4 – CALC[2:0] ADC Error Calculation Mode Select bits

See the table below for selection details.

Table 32-5. ADC Error Calculation Mode
CALC	Action During First Precharge Stage		Application
CALC	DSEN = `0` Single-Sample Mode	DSEN = `1` CVD Double-Sample Mode⁽¹⁾	Application
`000`	ADRES-ADPREV	ADRES-ADPREV	First derivative of single measurement⁽²⁾
`000`	ADRES-ADPREV	ADRES-ADPREV	Actual CVD result in CVD mode⁽²⁾
`001`	ADRES-ADSTPT	(ADRES-ADPREV)-ADSTPT	Actual result vs. setpoint
`010`	ADRES-ADFLTR	(ADRES-ADPREV)-ADFLTR	Actual result vs. averaged/filtered value
`011`	Reserved	Reserved	Reserved
`100`	ADPREV-ADFLTR	ADPREV-ADFLTR	First derivative of filtered value⁽³⁾ (negative)
`101`	ADLFTR-ADSTPT	ADFLTR-ADSTPT	Average/filtered value vs. setpoint
`110`	Reserved	Reserved	Reserved
`111`	Reserved	Reserved	Reserved
Note: When PSIS = `0`, the value of ADRES-ADPREV) is the value of (S2-S1) from the Computation Modes table. When PSIS = `0`. When PSIS = `1`.

Bit 3 – SOI ADC Stop-on-Interrupt bit

Value	Name	Description
`1`	CONT = `1`	GO is cleared when the threshold conditions are met, otherwise the conversion is retriggered
`0`	CONT = `1`	GO is not cleared by hardware, must be cleared by software to stop retriggers
`x`	CONT = `0`	This bit is not used

Bits 2:0 – TMD[2:0] Threshold Interrupt Mode Select bits

Value	Description
`111`	Interrupt regardless of threshold test results
`110`	Interrupt if ERR > UTH
`101`	Interrupt if ERR ≤ UTH
`100`	Interrupt if ERR < LTH or ERR > UTH
`011`	Interrupt if ERR > LTH and ERR < UTH
`010`	Interrupt if ERR ≥ LTH
`001`	Interrupt if ERR < LTH
`000`	Never interrupt

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