2.7 Buck Layout Guide
To achieve the best buck output voltage performance, it is mandatory to follow the layout recommendations as listed:
- The inductor and capacitor of buck circuit must be placed in the same layer and close to IS2083BM.
- Buck trace width must be at least 15 mils.
- Buck input – refer to Figure 2-1 and Figure 2-2 for IS2083BM pin K1 and K9. Place the buck input capacitor (C86) as close as possible to pin K1 (PMU_BK1_VDD) and K9 (PMU_BK2_VDD). The buck input routing path sequence is from SYS_PWR to C86, then connect C86 to pin K1 and K9. Do not connect SYS_PWR directly to pin K1 and K9 without first connecting to C86.
- Buck Output – refer to Figure 2-1 for IS2083BM pin K3 (BK1_O_1V5). The buck output routing path sequence is PMU_BK1_LX, L2, C87, PMU_BK1_VOUT and must be as short as possible. Trace of buck output to load must be connected from C87.
- Keep no ground trace under inductors L2 and L3 on top layer.
- Place solid ground plane on 2nd layer. The ground path from C87 and C88 to IS2083BM pins F5, F6 and E5 ground must be short and direct without being interrupted by another trace/traces. The ground of C87 and C88 must be placed at least a ground Via to the ground plane to reduce the ground impedance.
To ensure the buck output voltage quality, the wire wound coil high current inductor is recommended for buck inductor. The 10 uH wire wound inductor (ZWP-0805-100K) with high IDC and low DCR are recommended. The following figure is an example considered from ZenithTek.
Note: Multi-layer Ceramic Inductor (MLCI) is
not recommended to be used as L10
as it may not be able
to start up the chip stably. The poor yield rate also affects the quality of voltage.