3 PWM Timing and Control Overview

The PWM control scheme used to drive the circuit is based on a variable frequency 50% duty cycle push-pull configuration typical of a transformer application. A single cycle of one PWM output pair is shown in Figure 3-1.

Figure 3-1. Push-Pull PWM Output Waveform with Dead Time

Both the rising and falling edges of both outputs are independently controllable. Dead time is inserted between the transitions to avoid shoot-through scenarios. Expanding to a 3-phase interleaved system, Phases B and C are phase-shifted by 120º and 240º from Phase A, as shown in Figure 3-2.

Figure 3-2. Bank 1, 3-Phase PWM Timing, Primary

Figure 3-3 builds further and includes the PWM for Secondary Rectification (SR) control and their respective start-of-cycle (SOC) triggers. Additional phase offsets and duty cycle durations between the primary and secondary PGs are implemented but not shown in the figure for simplicity. The two banks of the system are then interleaved with a phase offset of 90º to complete the system of 24 switches, as shown in Figure 3-4. Bank 1 phases B and C are omitted to focus on the timing dependencies of Bank 2.

Figure 3-3. Bank 1, 3-Phase PWM Timing Diagram

Figure 3-4. Interleaved 3-Phase PWM Timing Diagram