6 PWM Data Update Scheme

The system control is based on variable frequency operation. Modifying the period requires special handling of the timing of data writes and when they are applied to the system. PWM1 and APWM1 are the 'masters' of the update system and broadcast the data update request to the other PGs within their respective peripheral group. Data updates occur at the start of the next PWM cycle.

The data registers are buffered to prevent write corruption. The data registers that reside in RAM SFR space, as defined in Table 4-1, are not directly used by the PWM. The PWM has its own copy of all the data registers that are used for PWM operation. This allows the SFRs to be written while the PWM is operating with its own copies. After all the data SFR writes are complete, the PWM can be requested to transfer the new data from the SFRs into the PWM.

Data from the ADC is used to compute the control parameters of the system. This is typically done in the interrupt service routine for the ADC and is asynchronous to the PWM. From the control parameters, the PWM register data can be computed and written. However, the software needs to ensure that the last cycle has completed before writing new values. This check is done by reading the PGs UPDATE status bits to ensure no updates are still pending. The timing of the PWM register writes is not dependent on the PWM cycle and can be done at any time. The timing of the update event is dependent and is scheduled using the PWM's interrupt. The last PG in the timing chain is used for this purpose. In the case of this example, PG8 is used, and its interrupt is configured to occur at its SOC. This gives maximum time for the PWM to complete the data transfer before the SOC of the first PG in the timing chain, PG1. Software writes the UPDREQ bits for PWM1 and APWM1 to initiate the transfer and subsequent use at the next SOC. Figure 6-1 summarizes the update process. Alternatively, the DMA can be used to automate setting update bits with its trigger as PG8 SOC.

After the control system calculates the new PWM switching frequency, the next PWM cycle timings (phase offsets, duty cycles, etc.) based on PWM resolution/ticks need to be calculated. In independent PWM mode of operation, the firmware must update almost 40 different PWM registers for this dual 3-phase interleaved solution. The calculations and PWM buffer updates take roughly 600 ns when the microcontroller is executing at 200 MHz. Figure 6-2 shows update timing in relation to the PWM signals.