4 Basic PWM Setup and Timing

All PWM channels are operated in independent edge PWM mode, dual output, with the output mode set to independent. This configuration allows true independent control of all PWM edge timings. This is mandatory, as it is common for the primary half-bridge FETs and SR FETs to need different pulse widths to account for gate driver delays and for optimizing zero current switching on the secondary side. The master data registers (MPER, MDC, MPHASE) are used across the PWM Generators (PGx) to simplify data updates. For the auxiliary PWM peripheral, the master registers AMPER, AMDC and AMPHASE are used to simplify data updates.

The edge timing shown in Figure 4-1 is defined by the following equations:

DTH = MPHASE

Duty Cycle High = MDC - MPHASE

DTL = PGxTRIGA – MDC

Duty Cycle Low = PGxTRIGB – PGxTRIGA

Refactored for the data values written by the FW:

MPER = Period

MPHASE = DTH

MDC = Duty Cycle High = MPER/2 (50% DC)

PGxTRIGA = MPER/2 + DTL

PGxTRIGB = MPER

PG1 is configured as the ‘master’ PG in the system. All edge timing is derived from PG1, including the phase offset event triggers and master data registers, MPER, MDC and MPHASE. PG1 is also the master of the data updates and broadcasts the update sync request to the other seven PGs within its group. APG1 is also an update master and broadcasts the update sync request to the other three APGs within its group.