31.5.4 ADCON3

ADC Control Register 3
Name: ADCON3
Address: 0x1D29

Bit 76543210 
  CALC[2:0]SOITMD[2:0] 
Access R/WR/WR/WR/W/HCR/WR/WR/W 
Reset 0000000 

Bits 6:4 – CALC[2:0] ADC Error Calculation Mode Select

Table 31-5. ADC Error Calculation Mode
CALCADERRApplication
DSEN = 0

Single-Sample Mode

DSEN = 1

CVD Double-Sample Mode(1)

111ReservedReservedReserved
110ReservedReservedReserved
101ADFLTR-ADSTPTADFLTR-ADSTPTAverage/filtered value vs. setpoint
100ADPREV-ADFLTRADPREV-ADFLTRFirst derivative of filtered value(3) (negative)
011ReservedReservedReserved
010ADRES-ADFLTR(ADRES-ADPREV)-ADFLTRActual result vs. averaged/filtered value
001ADRES-ADSTPT(ADRES-ADPREV)-ADSTPTActual result vs. setpoint
000ADRES-ADPREVADRES-ADPREVFirst derivative of single measurement(2)
Actual CVD result(2)
Note:
  1. When DSEN = 1 and PSIS = 0, ADERR is computed only after every second sample.
  2. When PSIS = 0.
  3. When PSIS = 1.

Bit 3 – SOI ADC Stop-on-Interrupt

ValueNameDescription
xCONT = 0This bit is not used
1CONT = 1GO is cleared when the Threshold conditions are met, otherwise the conversion is retriggered
0CONT = 1GO is not cleared by hardware, must be cleared by software to stop retriggers

Bits 2:0 – TMD[2:0] Threshold Interrupt Mode Select

ValueDescription
111Interrupt regardless of threshold test results
110Interrupt if ADERR > ADUTH
101Interrupt if ADERR ≤ ADUTH
100Interrupt if ADERR < ADLTH or ADERR > ADUTH
011Interrupt if ADERR > ADLTH and ADERR < ADUTH
010Interrupt if ADERR ≥ ADLTH
001Interrupt if ADERR < ADLTH
000Never interrupt