3.4 Hardware State Machines

The Finite State Machines form an important component of many user applications. Traditionally, these state machines are implemented as part of a software code executed by the CPU. However, the synchronous operation capability of the Signal Routing Port module allows these state machines to be implemented in the hardware, offloading the big task from the CPU and freeing it to perform other functions.

When operating as a state machine, the flip-flop in the synchronous path of the Signal Routing Port acts as the holding register for the current state. The following state and output functions for the state machine are implemented using a Configurable Logic Cell (CLC) peripheral, which integrates seamlessly with the Signal Routing Port. Figure 3-1 and Figure 3-2 below show how to use the Signal Routing Port and CLCs to form hardware-based Mealy and Moore State Machines.