Home
4 CPU Registers
This module contains functional safety diagnostics APIs for CPU Registers.
4.1 Defines
4.1.9 SPL_PATTERN

Introduction
This document contains API documentation for the diagnostic tests included MPLAB® Code Configurator AVR® IEC60730 Class B Diagnostic Library.
1 Software Requirements
2 Clock Frequency Test
This module contains functional safety diagnostics APIs for Clock Frequency test.
3 CPU Program Counter
This module contains functional safety diagnostics APIs for CPU Program counter test.
4 CPU Registers
This module contains functional safety diagnostics APIs for CPU Registers.
5 EEPROM - 16-bit CRC
This module contains APIs to calculate, store and validate 16-bit CCITT CRC for a given EEPROM region.
6 EEPROM - 32-bit CRC
This module contains APIs to calculate, store and validate 32-bit CCITT CRC for a given EEPROM region.
7 FLASH - 16-bit CRC
This module contains APIs to calculate, store and validate 16-bit CCITT CRC for a given FLASH region.
8 FLASH - 32-bit CRC
This module contains APIs to calculate, store and validate 32-bit CCITT CRC for a given FLASH region.
9 Interrupt Frequency Test
This module contains functional safety diagnostics API for Interrupt Frequency Test.
10 SRAM - Checkerboard Algorithm
This module contains functional safety diagnostics APIs for SRAM Checkerboard Test.
11 SRAM - March C-Minus Algorithm
This module contains functional safety diagnostics APIs for SRAM March-C Minus.
12 Simple Watchdog Timer
This module contains functional safety diagnostics APIs for WatchDog Timer Test.
13 Windowed Watchdog Timer
This module contains functional safety diagnostics APIs for WatchDog Timer Test.
14 File List
Here is a list of all documented files with brief descriptions
15 Class List
Here is a list of all documented files with brief descriptions

4.1.9 SPL_PATTERN

#define SPL_PATTERN ((SPL_CONFIGURABLE_BITS_BM & 0xAAU)+ INTERNAL_SRAM_START_8LSB)

Applies a checkerboard bit-pattern (0xAA) to the configurable bits of the SPL register. Because the configurable bits of SPL are dependent on the size of SRAM, it is necessary to add the start address to compensate for any non-configurable bits when reading and writing to the SPL register.