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4 CPU Registers
This module contains functional safety diagnostics APIs for CPU Registers.
4.1 Defines
4.1.8 SPL_CONFIGURABLE_BITS_BM

Introduction
This document contains API documentation for the diagnostic tests included MPLAB® Code Configurator AVR® IEC60730 Class B Diagnostic Library.
1 Software Requirements
2 Clock Frequency Test
This module contains functional safety diagnostics APIs for Clock Frequency test.
3 CPU Program Counter
This module contains functional safety diagnostics APIs for CPU Program counter test.
4 CPU Registers
This module contains functional safety diagnostics APIs for CPU Registers.
5 EEPROM - 16-bit CRC
This module contains APIs to calculate, store and validate 16-bit CCITT CRC for a given EEPROM region.
6 EEPROM - 32-bit CRC
This module contains APIs to calculate, store and validate 32-bit CCITT CRC for a given EEPROM region.
7 FLASH - 16-bit CRC
This module contains APIs to calculate, store and validate 16-bit CCITT CRC for a given FLASH region.
8 FLASH - 32-bit CRC
This module contains APIs to calculate, store and validate 32-bit CCITT CRC for a given FLASH region.
9 Interrupt Frequency Test
This module contains functional safety diagnostics API for Interrupt Frequency Test.
10 SRAM - Checkerboard Algorithm
This module contains functional safety diagnostics APIs for SRAM Checkerboard Test.
11 SRAM - March C-Minus Algorithm
This module contains functional safety diagnostics APIs for SRAM March-C Minus.
12 Simple Watchdog Timer
This module contains functional safety diagnostics APIs for WatchDog Timer Test.
13 Windowed Watchdog Timer
This module contains functional safety diagnostics APIs for WatchDog Timer Test.
14 File List
Here is a list of all documented files with brief descriptions
15 Class List
Here is a list of all documented files with brief descriptions

4.1.8 SPL_CONFIGURABLE_BITS_BM

#define SPL_CONFIGURABLE_BITS_BM (INTERNAL_SRAM_END_8LSB - INTERNAL_SRAM_START_8LSB)

Subtract the MSBs of the end address from the start address to find which bits are configurable in the SPL register, since some bits may always be 0 or 1 (i.e. non-configurable) depending on the SRAM location in the memory map.