4 Using the CLC to Create an LED Dimming Effect

This example shows an initialization of the CLC in the SR Latch mode for the implementation of an automatic fixed frequency with variable duty cycle PWM signal. The function is automatically called as it does not require code or core supervision to work. The hardware is set at start-up and can be reconfigured during run-time. The truth table of the SR Latch is shown below.

CLC1 (SR Latch) has Timer2 as S gate source (which creates the fixed frequency of the generated PWM), and connected at the R gate is Timer4 to generate the duty cycle of the PWM. Timer4 is set with a slightly higher frequency than Timer2. At each cycle, the duty cycle will get smaller with the difference between the two signals until it reaches zero and the process restarts. The difference between Timer2 and Timer4 represents the step of the duty cycle change, which in this case is 0.1 Hz (or 1 Least Significant Byte difference), and therefore creating 255 repetitive PWM signals.

When this PWM signal is connected to an LED, the created effect is that the LED is repetitively dimmed. If the signal is inversed, it creates the effect of repetitively increasing LED light (the kind of loading effect).

The internal architecture is shown in Figure 4-1.

Test setup configurations:

• Timer2 frequency = 24.41 Hz (4.096 ms period)
• Timer4 frequency = 24.51 Hz (4.08 ms period)
• CLC1 is set up as SR Latch

Figure 4-2 displays the CLC1 output implementing the fixed frequency with variable duty cycle function:

• Signal 2 (Green) is CLC1 output

To achieve the functionality described by the use case, the following actions will have to be performed:

• System clock initialization
• Port initialization
• Timer initialization
• CLC initialization.