1 Peripheral Overview

The Configurable Logic Cell (CLC) module provides programmable logic that operates outside the speed limitations of software execution. The CLC takes up to 64 input signals and, using configurable gates, reduces the 64 inputs to four logic lines that drive one of eight selectable single-output logic functions.

Input sources are a combination of the following components:
  • I/O pins
  • Internal clocks
  • Peripherals
  • Register bits

The output can be directed internally to peripherals and to an output pin.

Important: There are several CLC instances on this device. Throughout this section, the lower case x in register names is a generic reference to the CLC instance number (CLCx). For example, the first instance of the control register is CLC1CON and is generically described in this chapter as CLCxCON.

The following figure is a simplified diagram showing signal flow through the CLC.

Figure 1-1. CLC Simplified Block Diagram

Possible configurations include:

  • Combinatorial Logic:
    • AND
    • NAND
    • AND-OR
    • AND-OR-INVERT
    • OR-XOR
    • OR-XNOR
  • Latches:
    • S-R
    • Clocked D with Set and Reset
    • Transparent D with Set and Reset
    • Clocked J-K with Reset
Figure 1-2. Programmable Logic Functions

Programming the CLC module is performed by configuring the four stages in the logic signal flow. These stages are:

  • Data selection
  • Data gating
  • Logic function selection
  • Output polarity

Each stage is setup at run time by writing to the corresponding CLC Special Function Registers. This has the added advantage of permitting logic reconfiguration on-the-fly during program execution.