21.8.2 Hardware Gate Mode

The Hardware Gate modes operate the same as the Software Gate mode except the TMRx_ers external signal can also gate the timer. When used with the CCP, the gating extends the PWM period. If the timer is stopped when the PWM output is high, then the duty cycle is also extended.

When MODE[4:0] = 00001 then the timer is stopped when the external signal is high. When MODE[4:0] = 00010, then the timer is stopped when the external signal is low.

Figure 21-4 illustrates the Hardware Gating mode for MODE[4:0] = 00001 in which a high input level starts the counter.