5.6.2 OSCCON2

Oscillator Control Register 2
Note:
  1. The POR value is the value present when user code execution begins.
  2. The Reset value (q/q) is the same as the NOSC/NDIV bits.
  3. EXTOSC configured by the CONFIG1[FEXTOSC] bits.
  4. HFINTOSC frequency is set with the HFFRQ bits.
  5. EXTOSC must meet the PLL specifications.
Name: OSCCON2
Offset: 0xE44

Bit 76543210 
  COSC[2:0]CDIV[3:0] 
Access RRRRRRR 
Reset qqqqqqq 

Bits 6:4 – COSC[2:0]  Current Oscillator Source Select bits (read-only)(1,2)

Indicates the current source oscillator and PLL combination, as shown in the following table.

Table 5-5. COSC Bit Settings
COSC/NOSCClock Source
111EXTOSC(3)
110HFINTOSC(4)
101LFINTOSC
100SOSC
011Reserved
010EXTOSC + 4x PLL(5)
001Reserved
000Reserved

Bits 3:0 – CDIV[3:0]  Current Divider Select bits (read-only)(1,2)

Indicates the current postscaler division ratio, as shown in the following table.

Table 5-4. CDIV Bit Settings
CDIV/NDIVClock Divider
1111-1010Reserved
1001512
1000256
0111128
011064
010132
010016
00118
00104
00012
00001
The POR value is the value present when user code execution begins.The Reset value (q/q) is the same as the NOSC New Oscillator Source Request bits(1,2,3) /NDIV New Divider Selection Request bits(2,3) bits.EXTOSC configured by the CONFIG1[FEXTOSC] bits.HFINTOSC frequency is set with the HFFRQHFINTOSC Frequency Selection bits bits.EXTOSC must meet the PLL specifications.