29.3.1.6 Receive Overrun Error

The receive FIFO buffer can hold two characters. An overrun error will be generated if a third character, in its entirety, is received before RCxREG is read to access the FIFO. When this happens, the OERR bit of the RCxSTA register is set. Previous data in the FIFO will not be overwritten. The two characters in the FIFO buffer can be read; however, no additional characters will be received until the error is cleared. The OERR bit can only be cleared by clearing the Overrun condition. If the overrun error occurred when the SREN bit is set and CREN is clear, then the error is cleared by reading RCxREG. If the overrun occurred when the CREN bit is set, then the Error condition is cleared by either clearing the CREN bit of the RCxSTA register or by clearing the SPEN bit, which resets the EUSART.