18.2 PPS Outputs

Each I/O pin has a PPS register with which the pin output source is selected. With few exceptions, the port TRIS control associated with that pin retains control over the pin output driver. Peripherals that control the pin output driver as part of the peripheral operation will override the TRIS control as needed. These peripherals include:

  • EUSART (synchronous operation)
  • MSSP (I2C)

Although every pin has its own PPS peripheral selection register, the selections are identical for every pin as shown in RxyPPS.

Important: The notation “Rxy” is a placeholder for the pin identifier. The ‘x’ holds the place of the PORT letter and the ‘y’ holds the place of the bit number. For example, Rxy = RA0 for the RA0PPS register.

The table below shows detailed output routing options for each peripheral.

Table 18-3. Peripheral PPS Output Selection Codes
RxyPPSPin Rxy Output SourcePORT To Which Output Can Be Directed
0x21ADGRDBA—C————H
0x20ADGRDAA—C————H
0x1FDSM1A—C————H
0x1ECLKR—BC————H
0x1DTMR0—BC—————
0x1CMSSP2 (SDO/SDA)—B—D————
0x1BMSSP2 (SCK/SCL)—B—D————
0x1AMSSP1 (SDO/SDA)—BC—————
0x19MSSP1 (SCK/SCL)—BC—————
0x18CMP3A————FG—
0x17CMP2A————FG—
0x16CMP1A————FG—
0x15EUSART5 (DT)—B——E—G—
0x14EUSART5 (TX/CK)—B——E—G—
0X13EUSART4 (DT)—BC—————
0x12EUSART4 (TX/CK)—BC—————
0x11EUSART3 (DT)—B——E———
0x10EUSART3 (TX/CK)—B——E———
0x0FEUSART2 (DT)—B—D——G—
0x0EEUSART2 (TX/CK)—B—D——G—
0x0DEUSART1 (DT)—BCD————
0x0CEUSART1(TX/CK)—BCD————
0x0BPWM7A—C—E———
0x0APWM6A—C—E———
0x09CCP5—B——E—G—
0x08CCP4—B——E—G—
0x07CCP3—BC—E———
0x06CCP2—BC—E———
0x05CCP1—BC—E———
0x04CWG1D—B——E—G—
0x03CWG1C—BC—E———
0x02CWG1B—B——E—G—
0x01CWG1A—BC—E———
0x00LATxyABCDEFGH