11.1.4 Recommended Operating Conditions

Table 11-4. Power Supply Inputs
Power Input	Parameter	Conditions	Min	Max	Unit
VDDCPU⁽¹⁾	Cortex-A7 and cache memories	f_{CPU_CLK} ≤ 600 MHz	1.03	1.21	V
		f_{CPU_CLK} ≤ 800 MHz	1.12	1.21	V
		f_{CPU_CLK} ≤ 1 GHz⁽²⁾ (SAMA7G54-V/4HB or SAMA7G54-E/4HB only and T_J <= 105°C)	1.22	1.30	V
VDDCORE	Core logic power supply	Device in ULP0 (f < 25 MHz)⁽³⁾ or ULP1 mode	1.03	1.21	V
VDDCORE	Core logic power supply	–	1.12	1.21	V
VDDIODDR	SDRAM I/O lines power supply	[LPDDR2 / LPDDR3]-SDRAM	1.14	1.30	V
		DDR3-SDRAM	1.425	1.575	V
		DDR3L-SDRAM	1.283	1.45	V
		DDR2-SDRAM	1.7	1.9	V
VDDIN33⁽⁴⁾	VDDOUT25 regulator, backup power switch and OTP power inputs	–	3.0	3.6	V
VDDUTMII⁽⁴⁾	USB device and host UTMI+ interface	–	3.0	3.6	V
VDDDPHY⁽⁵⁾	MIPI D-PHY power supply	–	2.4	2.6	V
VDDANA⁽⁵⁾	ADC, comparator, temperature sensor, PLLs, main crystal oscillator, main RC oscillator power supply	–	2.4	2.6	V
VDDIOP[0,1]⁽⁶⁾	Peripheral I/O lines	–	1.7	3.6	V
VDDQSPI[0,1]⁽⁶⁾	QSPIx I/O lines	–	1.7	3.6	V
VDDSDMMC[0,1,2]⁽⁶⁾	SDMMCx I/O lines	–	1.7	3.6	V
VBAT	Backup supply input	–	1.7	3.6	V
t_{R_VDD}	Power supply slope at power-up	Applies to any of the power supply inputs listed above	0.2	20	mV/μs
t_{F_VDD}	Power supply slope at power-down	Applies to any of the power supply inputs listed above	-20	-1⁽⁷⁾	mV/μs

Note:

For lifetime estimation as a function of operating voltage and junction temperature, refer to the application note "SAMA7G5 Series Product Lifetime Estimation" (AN4532), available on www.microchip.com.
VDDCPU-related alarms in SECUMOD_SR are always triggered when f_{CPU_CLK} > 800 MHz.
In ULP0 mode, all PLLs are off. The maximum clock frequency in the system is 25 MHz: f_MAINCK < 25 MHz, f_{CPU_CLK} < 25 MHz, f_MCKx < 25 MHz.
VDDIN33 and VDDUTMII are powered from one single power source so that ΔV(VDDIN33,VDDUTMII) ≤ 50 mV.
VDDANA and VDDDPHY must be connected to VDDOUT25.
Supply range restrictions apply when using the digital peripheral timing characteristics. See I/O Characteristics.
For VBAT, this value is 0 mV/μs.

Table 11-5. Recommended Operating Conditions on Input Pins⁽¹⁾
Symbol	Parameter	Conditions	Min	Max	Unit
V_IN	Input line voltage range on inputs⁽²⁾⁽³⁾	–	-0.3	V_DD+ 0.3	V
I_IN	DC current injection on inputs⁽⁴⁾⁽⁵⁾	–	–	± 0.2	mA
I_{TOT_INJ}	Total current injection per power rail or per ground rail⁽⁶⁾	–	–	± 2	mA

Note:

In this table, VDD refers to the voltage of the associated power rail of the I/O line, as defined in the table Pin Description. Ex: for PA12, VDD refers to VDDIOP0.
Input voltages V_IN ≤ 0V or V_IN ≥ VDD lead to negative or positive current injection on inputs.
For A/D converter analog inputs (PC13..PC24, PC30, PC31, PD0, PD1), input voltages V_IN≥ min(V_DDANA, V_ADVREFP) lead to saturated A/D conversion to 0xFFF.
Current injection on A/D converter analog inputs (PC13..PC24, PC30, PC31, PD0, PD1) may degrade the analog performance of the corresponding channel, or the analog performance of other analog channels.
High frequency current injection must be limited to avoid propagating high frequency signals to internal sensitive analog circuits (oscillators, regulators, etc.). One common use case of high frequency current injection occurs when a digital input pin suffers overshoots and/or undershoots from a poorly adapted transmission line (PCB trace with signal reflections, for example). These cases should be cured by appropriate source series resistor termination. Special attention must be paid to high speed interfaces (Gigabit Ethernet MAC I/F, SD card or e.MMC I/F, QSPI I/F, etc.).
Corresponds to the sum of the positive currents into one power rail and respectively to the sum of the negative currents into one ground rail as defined in the table Pin Description.

Table 11-6. Recommended Operating Conditions on Internal Clocks
Symbol	Parameter	Conditions	Min	Max	Unit
f_{CPU_CLK}	Processor clock (CPU_CLK) frequency	V_DDCPU ≥ 1.22V (SAMA7G54-V/4HB or SAMA7G54-E/4HB only and T_J ≤ 105°C)	–	1000	MHz
		V_DDCPU ≥ 1.12V	–	800	MHz
		V_DDCPU ≥ 1.03V	–	600	MHz
f_MCK0	Main system bus clock (MCK0) frequency	–	–	200	MHz
f_MCK1	Main system bus clock (MCK1) frequency	–	–	200	MHz
f_MCK2	Main system bus clock (MCK2) frequency	–	–	533	MHz
f_MCK3	Main system bus clock (MCK3) frequency	–	–	266	MHz
f_MCK4	Main system bus clock (MCK4) frequency	–	–	400	MHz

Table 11-7. Recommended Operating Conditions on SDRAM Interface
Symbol	Parameter	Conditions	Min	Max	Unit
f_{DDR_CLK}	SDRAM clock frequency	[LPDDR2 / LPDDR3]-SDRAM	100	533	MHz
		[DDR3 / DDR3L]-SDRAM	100	533	MHz
		DDR2-SDRAM	125	533	MHz

Table 11-8. Recommended Thermal Operating Conditions⁽¹⁾⁽²⁾
Symbol	Parameter	Conditions		Min	Max	Unit
T_J	Junction temperature range	Ordering code SAMA7G54(T)-V		-40	105	°C
T_J	Junction temperature range	Ordering code SAMA7G54(T)-E		-40	125	°C

Note:

For lifetime estimation as a function of operating voltage and junction temperature, refer to the application note "SAMA7G5 Series Product Lifetime Estimation" (AN4532), available on www.microchip.com.
The package characteristics in the table above are provided according to the JEDEC JESD51-2 standard with the 2s2p board and 0 m/s air flow. These values are not directly applicable to the final application. As per JEDEC standards, these parameters represent the device mounted on a specific PCB under controlled conditions. In real-world applications, the PCB design and construction, airflow, and other factors may significantly impact thermal characteristics.

Table 11-9. BGA343 Package Thermal Characteristics⁽¹⁾⁽²⁾
Symbol	Parameter	Typ	Unit
R_JA	Junction-to-ambient thermal resistance	25	°C/W
R_JB	Junction-to-board thermal resistance	18	°C/W
R_JC	Junction-to-case thermal resistance	8	°C/W
Ψ_JT	Junction-to-package-top characterization parameter	0.3	°C/W

Note:

According to the JEDEC JESD51-2 standard, with 2s2p board and 0 m/s air flow.
These values are not directly applicable to the board where the device is mounted. As per JEDEC standards, these parameters do not characterize the package itself but rather the package together with the PCB (4-layer or more) and other environmental factors (still air, etc.). For example, in still-air JEDEC-defined R_JA measurements, almost 70%–95% of the power generated by the chip is dissipated from the test board, not from the surfaces of the package.