3.3 Accessing the PCIe Bridge Register in the High-speed Serial Interface

The PCIe Bridge registers must not be accessed before the PHY is ready. Wait for the PHY_READY signal (which indicates that the PHY is ready) to be asserted before updating the PCIe Bridge registers.

The PHY_READY signal is normally asserted within 200 μs after the device is powered up. Wait for 200 μs before accessing the PCIe Bridge registers.